The computer industry seeks ever advancing improvements in the performance of processors and memory. For processors, industry seeks ever-increasing clock speeds and processing throughput with reduced power consumption. For semiconductor memory, industry seeks increasing capacity, lower error rates, and increased durability. Semiconductor memory devices utilizing nanocrystals provide several technical advantages over other charge-storing memory devices. However, the performance of memory devices utilizing nanocrystals can degrade over time.
In particular, nanocrystals can be used in electrically erasable programmable read only memory (EEPROM) structures, which can be used in integrated circuits for non-volatile data storage. EEPROM device structures can include a polysilicon floating gate formed over a tunnel dielectric, which is formed over a semiconductor substrate, to store charge. As device dimensions and power supply voltages decrease, the thickness of the tunnel dielectric cannot correspondingly decrease in order to prevent data retention failures. An EEPROM device using isolated silicon nanocrystals or nanoparticles as a replacement to the floating gate does not have the same vulnerability to isolated defects in the tunnel dielectric and thus, permits scaling of the tunnel dielectric and the operating voltage without compromising data retention.
But, the programming and erasing cycling of nanocrystal memory can trap electrons in the bit cell stack including the floating gate and can and increase the erase voltage. Over time, increased trapping can result in increased read voltage, which can result in degraded read performance.
As such, improved nanocrystal memory devices would be desirable.
The use of the same reference symbols in different drawings indicates similar or identical items.